#ifndef _CP_H
#define _CP_H
/*
  author Sylvain Bertrand <digital.ragnarok@gmail.com>
  Protected by GNU Affero GPL v3 with some exceptions.
  See README at root of alga tree.
*/
#define CP_RING_LOG2_QWS 17
#define CP_RING_DW_MASK ((1 << CP_RING_LOG2_QWS) * 2 - 1)

#define CP_RING_PFP_DWS 16
#define CP_RING_PFP_DW_MASK (CP_RING_PFP_DWS - 1)

#define	PKT_TYPE2	2
#define	PKT_TYPE3	3
#define PKT2		(PKT_TYPE2 << 30)
#define PKT3(op,n)	((PKT_TYPE3 << 30) \
			| (((op) & 0xff) << 8) \
			| ((n - 1) & 0x3fff) << 16)

/* packet 3 operations */
#define	PKT3_CLR_STATE				0x12
#define PKT3_MODE_CTL				0x18
#define PKT3_CTX_CTL				0x28
#define PKT3_IB					0x32
#define	PKT3_SURF_SYNC				0x43
#define		PKT3_CB0_DST_BASE_ENA			BIT(6)
#define		PKT3_CB1_DST_BASE_ENA			BIT(7)
#define		PKT3_CB2_DST_BASE_ENA			BIT(8)
#define		PKT3_CB3_DST_BASE_ENA			BIT(9)
#define		PKT3_CB4_DST_BASE_ENA			BIT(10)
#define		PKT3_CB5_DST_BASE_ENA			BIT(11)
#define		PKT3_CB6_DST_BASE_ENA			BIT(12)
#define		PKT3_CB7_DST_BASE_ENA			BIT(13)
#define		PKT3_DB_DEST_BASE_ENA			BIT(14)
#define		PKT3_CB8_DST_BASE_ENA			BIT(15)
#define		PKT3_CB9_DST_BASE_ENA			BIT(16)
#define		PKT3_CB10_DST_BASE_ENA			BIT(17)
#define		PKT3_CB11_DST_BASE_ENA			BIT(18)
#define		PKT3_FULL_CACHE_ENA			BIT(20)
#define		PKT3_TC_ACTION_ENA			BIT(23)
#define		PKT3_VC_ACTION_ENA			BIT(24)
#define		PKT3_CB_ACTION_ENA			BIT(25)
#define		PKT3_DB_ACTION_ENA			BIT(26)
#define		PKT3_SH_ACTION_ENA			BIT(27)
#define		PKT3_SX_ACTION_ENA			BIT(28)
#define	PKT3_ME_INIT				0x44
#define		PKT3_ME_INIT_DEV_ID(x)			((x) << 16)
#define	PKT3_PREAMBLE_CTL			0x4a
#define		PKT3_PREAMBLE_BEGIN_CLR_STATE		(2 << 28)
#define		PKT3_PREAMBLE_END_CLR_STATE		(3 << 28)
#define	PKT3_SET_CFG_REG			0x68
#define		PKT3_SET_CFG_REG_START			0x00008000
#define		PKT3_SET_CFG_REG_END			0x0000ac00
#define	PKT3_SET_CTX_REG			0x69
#define		PKT3_SET_CTX_REG_START			0x00028000
#define		PKT3_SET_CTX_REG_END			0x00029000
#define	PKT3_SET_RES				0x6d
#define		PKT3_SET_RES_START			0x00030000
#define		PKT3_SET_RES_END			0x00038000
#define	PKT3_SET_SAMPLER			0x6e
#define		PKT3_SET_SAMPLER_START			0x0003c000
#define		PKT3_SET_SAMPLER_END			0x0003c600
#define	PKT3_SET_CTL_CONST			0x6f
#define		PKT3_SET_CTL_CONST_START		0x0003cff0
#define		PKT3_SET_CTL_CONST_END			0x0003ff0c

struct cp
{
	spinlock_t lock;

	unsigned wptr; /* dword index in ring buffer: accounted by CPU */
	unsigned rptr; /* dword index in ring buffer: accounted by GPU */
};

void cp_stop(struct pci_dev *dev);
void cp_init(struct pci_dev *dev);
void cp_me_init(struct pci_dev *dev);
void cp_gpu_state_init(struct pci_dev *dev);
void cp_wr(struct pci_dev *dev, u32 v);
void cp_commit(struct pci_dev *dev);
#endif /* CP_H */
